1. Field of the Invention
The present invention relates to an image display device using a liquid crystal element, an organic EL (Electro Luminescence) element, or the like, and more specifically to an image display device having a level shift circuit in an output section of a drive circuit.
2. Description of the Related Art
An image display panel using a liquid crystal element, an organic EL element, or the like includes a TFT (Thin Film Transistor) formed on a transparent board and has a pixel circuit configured with the TFT element, a data driver, a gate driver, and a protection circuit. A control signal for driving the data driver and the gate driver is transmitted from an external system via an FPC (Flexible Printed Card) to inside of the image display panel, while a data signal transmitted to the pixel circuit is further transmitted via a driver IC to inside of the image display panel.
Here, there is a problem that an operating voltage for an external system is different from that for the TFT circuit prepared inside the image display panel. (Generally, the operating voltage for the TFT circuit inside an image display panel is higher than that for an external system). To overcome this problem, a voltage level for a control signal such as a gate driver control signal or a data driver control signal is changed from an operating voltage for the external system to that for the TFT circuit inside a panel by using a level shift circuit formed with a mono-crystalline silicon transistor formed on the external system or a level shift circuit formed with a TFT inside the image display panel. A driver IC is subjected to level change in the output stage.
FIG. 11 illustrates a general configuration of a level shift circuit provided outside a display panel in an image display module which is currently produced (The configuration is disclosed, for instance, in JP-A-2003-283326). This circuit actuates a gate of an NMOS transistor NM7 by applying an input signal via an inverter INV1 and an inverter INV2 to the gate of the NMOS transistor NM7, and also actuates a gate of an NMOS transistor NM8 by applying an inversion signal for the input signal via the inverter INV1 to the gate of the NMOS transistor NM8.
In the following description, it is assumed that the NMOS transistor NM7 and the PMOS transistor PM8 are non-conductive to each other and also that the NMOS transistor NM8 and a PMOS transistor PM7 are conductive to each other. When an input signal voltage rises and surpasses a threshold value for the NMOS transistor NM7, the NMOS transistor NM7 is set in the conducting state. When an inversion signal voltage for an input voltage falls and becomes lower than a threshold value for the NMOS transistor NM8, the NMOS transistor NM8 is set in the non-conducting state. In this step, since the PMOS transistor PM7 is in the conducting state, a potential at a node ND9 is decided according to a conduction resistance ratio between the NMOS transistor NM7 and the PMOS transistor PM7.
When this potential falls down to a level lower than the threshold value for the PMOS transistor PM8 and the PMOS transistor PM8 is set in the conducting state, a value at the node DN10 rises toward a H (high) level voltage (H level voltage in the figure is VDD2), so that the PMOS transistor PM7 is set in the non-conducting state and a value at a node ND9 falls toward a L (low) level voltage (level voltage in the figure is a ground potential (GND)). Namely, the circuit functions as a level shift circuit which converts a low amplitude signal transmitted from a circuit using a low power voltage VDD1 to a high amplitude signal and transmits the high amplitude signal to a circuit using a high power voltage VDD2.
The level shift circuit shown in FIG. 11 is excellent in high speed operation and low current consumption although the level shift circuit has a small number of transistors. In addition, voltages applied to a source and a back gate of a transistor constituting the circuit shown in FIG. 11 are always kept equal, so that a parasitic diode D1 shown in FIG. 5B illustrating a cross-sectional structure of an NMOS transistor expressed with a transistor symbol in FIG. 5A or a parasitic diode D2 as shown in FIG, 7B illustrating a cross-sectional structure of a PMOS transistor expressed by a transistor symbol in FIG. 7A is always kept OFF, so that the substrate bias effect is never generated. Because of the feature, the level shift circuit is also excellent in operations at a low temperature, and is one of monocrystal silicon circuits which are most generally used.
The circuit shown in FIG. 12A is disclosed in JP-A-2000-187994. This circuit is configured with a thin film transistor (TFT). Applied to a gate electrode of a NMOS transistor NM13 is a voltage at the node 12 decided according to a conduction resistance ratio between a NMOS transistor NM10 and a PMOS transistor PM10. Applied to a gate electrode of a NMOS transistor NM14 is a voltage at a node ND11 decided according to a conduction resistance ratio between a NMOS transistor NM9 and a PMOS transistor PM9. When the NMOS transistor NM9 is shifted from the non-conducting state to the conducting state, also the NMOS transistor NM13 is shifted from the non-conducting state to the conducting state. When the NMOS transistor NM10 is shifted from the non-conducting state to the conducting state, also a NMOS transistor NM14 is shifted from the non-conducting state to the conducting state. These shifting operations occur alternately.
Conductivity resistance of a NMOS transistor is decided by the NMOS transistor NM9 and the lower cabinet 13 or by the NMOS transistor NM10 and the NMOS transistor NM14. A high amplitude signal with the L level at GND and the H level at the high power voltage VDD is input to gate electrodes of the NMOS transistor NM13 and the NMOS transistor NM14, so that a circuit operation can be realized with a small gate width. Therefore the circuit can be incorporated in a panel.
The circuit shown in FIG. 13 is formed with a monocrystal silicon semiconductor. In the circuit shown in FIG. 13, a voltage at the node 13 decided by a conduction resistance ratio between a NMOS transistor NM17 and a PMOS transistor PM11 is applied to a gate electrode of a NMOS transistor NM19, while a voltage at a node ND14 decided by a conduction resistance ratio between a NMOS transistor 18 and a PMOS transistor PM12 is applied to a gate electrode of a NMOS transistor NM20.
When the NMOS transistor NM17 is shifted from the non-conducting state to the conducting state, also a NMOS transistor NM 20 is shifted from the non-conducting state to the conducting state, while, when the NMOS transistor 18 is shifted from the non-conducting state to the conducting state, also a NMOS transistor NM19 is shifted from the non-conducting state to the conducting state, and there operations occur alternately. In this circuit, even when the circuit is in the initial state and the capability to drive the NMOS transistor NM17 and the NMOS transistor 18 is small, a difference is generated between a voltage appearing at the node ND 13 and that appearing at the node ND14, so that the circuit operates regularly. As an example of the level shift circuit having the configuration as described above is disclosed, for instance, in JP-A-2004-228879.
FIG. 14 illustrates a level shift circuit described in JP-A-2003-115758. This circuit realizes level shift by using the principle of a charge pump. This circuit requires a clock signal CLK and an inversion signal /CLK, and is configured with a TFT circuit. Because of the circuit configuration, when the circuit is formed with a monocrystal silicon semiconductor, a NMOS transistor NM23 is affected by the substrate bias effect. An input signal is received via a transistor NM21 for switching at a gate terminal of a NMOS transistor NM22, so that it is necessary to hold a threshold voltage for the NMOS transistor NM22 at a low level for raising a voltage of an input signal at a low voltage. When the circuit is formed with a TFT, a limit for operations at a low voltage is decided by a threshold value for the TFT, but since there is no influence by the substrate bias effect even when the NMOS transistor NM22 is replaced with a monocrystal silicon semiconductor having a lower threshold value that that for the TFT, it is considered that operations at a low voltage can be realized by the replacement.
However, there are several problems in the general level sift circuit shown in FIG. 11. Voltages at a node DN9 and a node ND10 is decided by a ratio between a conduction resistance of the NMOS transistor and that of the PMOS transistor, namely a ratio of drive capabilities of the two transistors.
In the PMOS transistors PM7 and PM8, a voltage at the source electrode is fixed at the high power voltage VDD2, and a high amplitude signal with the L level at GND and the H level at the high power voltage DD2 is input, while, in the NMOS transistors NM7 and NM8, a voltage at the source electrode is fixed at the GND voltage, and a low amplitude signal with the L level at the GND and the H level at the lower power voltage VDD1 is input to the gate electrode, and therefore in the monocrystal silicon semiconductor in which the lower power voltage VDD1 has been becoming more and more lower, or in the TFT circuit in which a threshold value Vth is large, a difference between voltages applied to the gate electrode and the source electrode is large, so that the capability for driving the NMOS transistors NM7 and NM8 is low. In this case, conduction resistance of the NMOS transistor becomes lower, and the PMOS transistor PM8 is not shifted by a voltage at the node ND9 from the non-conducting state to the conducting state, or the PMOS transistor PM7 is not shifted from the non-conducting state to the conducting state by the voltage at the node ND10. To set the ratio of driving capabilities at a proper level so the PMOS transistor PM8 properly operates even with high frequency waves, it is necessary to make a gate width of the NMOS transistor larger than that of the PMOS transistor.
The characteristic line shown in FIG. 15 represents sizes of the NMOS transistors NM1, NM2 required for quadrupling output for the VDD 1 of 2.5 V and for the VDD 2 of 10 V under the conditions in which a threshold voltage Vth for the transistor is 1 V and a load of 0.1 pF is applied to an output terminal of the level shift circuit. In FIG. 15, the horizontal axis represents an operating frequency [MHz] and the vertical axis represents a ratio of a channel length L of a MOS transistor and a channel width W thereof (W/L). For instance, for the NMOS transistor to operate at a frequency of 50 MHz, the transistor size expressed by W/L is required to be 490/4 or more. TO achieve the requirement above, an area of the input circuit section becomes larger, which disadvantageously drops the yield.
In the circuit shown in FIG. 12A (JP-A-2003-283326), in the state where the clock signal CK is fixed at the H level and the NMOS transistors NM11 and NM12 are always conducted to each other, if drive capabilities of the NMOS transistor NM9 and the NMOS transistor NM10 are small, the conduction resistance is high in both the NMOS transistor NM9 and the NMOS transistor NM10 and a voltage difference is not generated between a voltage at the node ND11 and the node ND12, so that both the NMOS transistor NM13 and the NMOS transistor NM14 are set in the conducting state, and both the voltage at the node ND11 and the voltage at the node ND12 drop to the L level, which sometimes disable operations of the circuit. To prevent occurrence of this problem, a control signal for a clock signal CK from the outside as well as for an inversion signal /CK is used, and the circuit is run correctly by transmitting the signals CK and /CK to prevent both the voltage at the node ND11 and the voltage at the node ND12 from dropping to the L level due to influence by the NMOS transistors NM15 and NM16 even when both the NMOS transistors NM13 and NM14 are in the conducting state.
In the circuit configuration shown in FIG. 12B, it is disadvantageously required to employ the clock signal CK from the outside and the inversion signal /CK. In order to lower conduction resistances in the NMOS transistors NM9, NM11, NM13 and NM 15 or in the NMOS transistors NM10, NM12, NM14 and NM16 and to set a ratio of the drive capabilities at the optimal value, it is necessary that amplitudes of the clock signal CK and the clock inversion signal /CK should be large, and therefore it is difficult to apply the circuit configuration to a TFT circuit having a large threshold value or a circuit requiring an input signal with low voltage and small amplitude.
Since the circuit shown in FIG. 13 is formed with a monocrystal silicon semiconductor, the circuit is affected by the substrate bias effect, and threshold values for the NMOS transistors NM19 and the NMOS transistor NM20 increase, so that sufficient drive capabilities are not generated, and the conduction resistance decided by a combination of the NMOS transistor NM17 and the NMOS transistor NM20 or by a combination of the NMOS transistor 18 and the NMOS transistor NM19 does not drop sufficiently, which is another problem to be solved.
The characteristic line F13_1 shown in FIG. 15 represents sizes of the NMOS transistors NM17, NM18 required when the ratio of a channel width W versus a channel length L (W/L) is 4/4, the work function (2φF) is equal to 0.7, the substrate bias effect coefficient γ is 0.3, and outputs for the VDD1 of 2.5 V and for the VDD2 of 10 V is to be quadrupled under the conditions in which a threshold value Vth for the transistor is 1 V and a load of 0.1 pF is applied to an output terminal of the level shift circuit. For instance, to operate with a frequency of 50 MHz, the transistor size W/L of 450/4 or more is required. The horizontal axis in FIG. 15 represents an operating frequency f [MHz].
The characteristic line F13_2 shown in FIG. 16 represents sizes of the NMOS transistor NM19 and the NMOS transistor NM20 when operating at a frequency of 50 MHz under the same conditions as those described above. Even when a transistor size as expressed by W/L of each of the NMOS transistor NM19 and the NMOS transistor NM20 is 16/4, the transistor size W/L is required to be 300/4 or more. To overcome the problem, the NMOS transistor NM17 and the NMOS transistor 18 are replaced with PMOS transistors to avoid the influence by the substrate bias effect. However, since there is still the problem that a drive capability of the PMOS transistor is smaller as compared to that of the NMOS transistor and cannot supply a sufficient voltage to a section between a gate and a source of the PMOS transistor. Also, in a low voltage monocrystal silicon semiconductor circuit or in a TFT circuit having a large threshold value, the problem relating to the necessity for a large area is not solved, and also the problem of low yield still remains.
In the circuit configuration shown in FIG. 14, the operating speed is decided by the conduction resistance of a NMOS transistor NM21 and a time constant for a capacitor C1, and is limited by a threshold value for the NMOS transistor NM21. When the NMOS transistor NM21 is replaced with a monocrystal silicon semiconductor, influence by the substrate bias effect is generated, and the effect of the replacement cannot be expected.